As the interconnect density and the operational frequency in a chip increase, the extraction of interconnect parasitics becomes more and more time consuming. This is particularly true if one were to target the extraction of 3-D (three-dimensional) parasitics, and the problem becomes even more complex if one attempts to extract capacitance and inductive parasitics. Inductive extraction is exceedingly time consuming, and accurate results are difficult to obtain. The accuracy cannot be compromised for critical nets, leaving little choice when using conventional extraction procedures, wherein extraction times typically comprise 50% of the design verification process.
In the past, it was sufficient to analyze device delays in great detail while performing crude estimates of interconnect delay for timing closure. By way of example, for noise closure, it was sufficient to isolate nets and perform a SPICE or ASTAP simulation. In view of the shrinkage of IC devices coupled to an increase of dynamic logic and the presence of interconnects having high aspect ratios (which are more densely packed), it becomes increasingly important to analyze interconnect lines as well as devices. Large interconnect parasitics clearly play an important role in the delay and noise. Accordingly, it is important to characterize device parasitics as well as interconnect parasitics. Parasitic inductance is also becoming increasingly relevant as clock frequencies increase and wire resistance decreases. Moreover, it is important to have this characterization available early in the design phase.
FIG. 1 illustrates the various stages taking place during the design of a chip, wherein parasitic information that was previously extracted is now utilized for predicting chip timing and noise. Information pertaining to interconnects becomes only known in the last phase, and more particularly, once the physical design has been completed and a detailed wiring of the chip is available.
Practitioners of the art will realize that a conventional physical design (PD) phase, typically consists of a floorplanning stage, a placement stage, and is followed by a wiring phase.
Floorplanning (10) consists of very large-scale positioning, sizing and shaping of the largest circuit blocks and functional units of a chip. This is done with the goal of minimizing timing delay, die area, power consumption and noise. During the floorplanning stage, wires connecting different blocks are not laid out and are thus unknown. At best, delay and noise levels (15) can be estimated so that a better layout can ultimately be chosen. This is achieved by using a probabilistic approach to estimating the environment.
Placement (20) involves moving (placing) circuit blocks within the chip. It is similar to floorplanning in its goals of minimizing power, delay, area and noise. Yet, it differs in that the units that are moved around are smaller, and the overall size and shape of the larger units are fixed. Wiring is still not defined at this point.
During the second stage of the PD stage, and more specifically, during chip/noise verification phase (18), the speed and accuracy of the post-wiring parasitic extraction are critical. During earlier stages of the design, e.g., following floor-planning and placement, but prior to initiating the detailed wiring phase, "approximate" parasitic information based on assumed routing, e.g., a Stiner tree routing (defined as a rectilinear, Manhattan routing connecting all the pins of a net), is helpful in predicting timing and noise information. This approximate information is obtained using probabilities of the presence or absence of surrounding wires, given a certain routing pattern. For both applications, a rapid computation of self and mutual capacitances and inductances in a true 3-Dimensional sense (3-D) is required.
At the wiring stage (30), the blocks laid out during floorplanning and placement are connected with wires (also referred to as interconnects). The exact positioning of the wires is done to minimize delay and noise, both increasing with coupling and self-capacitance.
Self and coupling parasitics of an interconnect wire in its environment are required at this point. By definition, this necessitates a 3-Dimensional analysis involving the specification of surrounding conductors within a certain physical window. The inherent time required to compute capacitance and inductance using a numerical field solver technique precludes it from being used during the extraction process. [Note: a field solver is an algorithmic solution in which an electrostatic and magnetostatic problem are solved using a numeric technique such as a finite element method or a boundary element method]. Approximate two-dimensional equations are very fast, but they yield solutions plagued with high inaccuracies (i.e., as much as 50%-100% in some cases). Crude table look-up overlapping conductors have been accounted for by using Boolean functions which, typically, determine the presence or absence of simple 3-D structures, modeling these structures, storing results in a table, and "adding" the results. This approach leads to inherent inaccuracies because the capacitance of a system of conductors cannot be computed by linear superposition of the capacitances of a subset of the conductors.
Wherever a rapid and accurate extraction is required, one approach is to break-up a 3-D interconnect configuration into a grid on n.times.n wires, the minimum value being n=3. If parasitics could be pre-computed for each pattern using a field solver, which would then be stored in a library, it would be possible to query this database on-the-fly to obtain parasitic with greater speed and with the equivalent accuracy of a field solver. This conventional approach, however, suffers from serious drawbacks, namely:
1) In a "pattern" based approach, in order to obtain an acceptable accuracy (e.g., &lt;5%), it is important to consider all vertical layers forming the IC semiconductor chip. For technologies having more than three metalized layers, the number of 3-D configurations in a library quickly expands to unmanageable proportions. By way of example, a typical 5.times.5.times.5 grid such as shown in FIG. 2, would have 2.sup.24 patterns in the database. Using a field solver, such as a database, may take as long as 250 days to generate.
2) The ability of handling off-grid wires and wires of arbitrary width which results in the generation of an infinite number of patterns.
In summary, until now conventional methods made use of crude pattern-recognition for technologies not exceeding three metalized layers, using two-dimensional approximations with three dimensional correction terms, and the summation of simple 3-D primitives. These techniques are proving insufficient to handle VLSI products of sub-micron dimensions.